1. Field of the Invention
Generally, the subject matter disclosed herein relates to the formation of integrated circuits, and, more particularly, to patterning dielectric materials used in metallization layers by means of sophisticated lithography and anisotropic etch techniques.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these devices in terms of speed and/or power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip, thereby typically requiring a plurality of stacked wiring levels or metallization layers to accommodate the required number of interconnect structures. The wiring levels typically comprise metal lines, which are connected to metal regions and metal lines of adjacent metallization layers of the wiring layer stack by vertical contacts, also referred to as vias.
In advanced integrated circuits, a limiting factor of device performance may be the signal propagation delay caused by the switching speed of the transistor elements and the electrical performance of the wiring levels of the devices, which may be determined by the resistivity (R) of the metal lines and parasitic capacitance (C) that may depend on spacing of the interconnect lines, since the line-to-line capacitance is increased in combination, while a reduced conductivity of the lines may result from their reduced cross-sectional area. While in some metallization levels, the RC time constants are the predominant factor that determines the overall performance, in other levels, a high series resistance of the metal lines due to design restriction in view of the line width may result in high current densities, which may lead to degraded performance and reduced reliability clue to increased electromigration, i.e., a current induced material flow caused by high current densities.
Traditionally, metallization layers are formed in a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride, with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities than may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by copper or copper alloys, which have a significantly lower electrical resistance and a higher resistivity against electromigration. Moreover, a further decrease of the parasitic RC time constants may be achieved by replacing the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>5) by so-called low-k dielectric materials. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper metallization layer is associated with a plurality of issues to be dealt with.
For example, copper and alloys thereof may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Therefore, the so-called damascene or inlaid technique is frequently employed in forming metallization layers including copper-based lines. Typically, in the damascene technique, the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper by plating methods, such as electroplating or electroless plating. In many damascene strategies, the openings for the vias and the metal lines are formed first and the metal is subsequently filled in during a common deposition process.
Due to the ongoing shrinkage of device features of the transistor elements, and since typically the number of interconnections between the respective circuit elements is greater than the number of circuit elements, a moderately high number of stacked metallization layers have to be provided, wherein the interlayer connection may be provided by respective vertical connections or vias, as previously explained. The conventional damascene approach involves the lithographical patterning of a resist layer, which in turn may be used for patterning a hard mask material since, in highly advanced lithography techniques, short wavelength exposure radiation may be used in combination with respective resist materials, which may have to be applied with a reduced thickness, thereby typically not allowing a direct patterning of the interlayer dielectric material merely on the basis of a resist mask. In particular, the patterning of the vertical interlayer connections, i.e., the vias, having an aspect ratio of 5 and higher with a lateral dimension of approximately 100 nm and less, represent a technological challenge to reliably form the via openings and subsequently fill the openings along with respective trenches that are formed in an upper portion of the interlayer dielectric material. For example, well-established strategies are known as “via first, trench last” or “trench first, via last” approaches, in which, in the former approach, the via openings are formed on the basis of a lithography process followed by an anisotropic etch process. Thereafter, the trench is formed on the basis of a respective lithography mask and subsequently this mask is used for etching a portion of the interlayer dielectric material to provide the trench that connects to the previously formed via opening. In the latter approach, the trench may be formed first on the basis of lithography and etch techniques, followed by a lithography process to define a via portion within the trench and subsequently perform an anisotropic etch process to actually form the via opening through the entire interlayer dielectric material. Consequently, a plurality of complex interrelated process steps are typically required in conventional strategies according to a dual inlaid technique, which, however, provides efficient metal deposition processes, since thereafter any barrier materials and the highly conductive metal may be formed in the via opening and the trench in a common process sequence.
However, in view of enhanced device reliability, in particular of the metallization system of advanced semiconductor devices, the continuous drive for reducing critical feature sizes may result in significantly increased complexity and thus non-uniformities of the critical patterning process, in particular in the formation of the via openings, which may therefore result in performance degradation of the metallization system and thus of the entire integrated circuit.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.